Overview

The aim of this unit is to equip students with the required engineering skills to design and implement integrated circuits, with an emphasis on front-end design. The objectives of this unit are to expose students to techniques and design methodologies in integrated circuit design. Students will develop skills in modelling, simulation, verification, testing, and implementation using industry-standard Electronic Design Automation (EDA) tools. Upon satisfactory completion of this unit, students should be able to carry out the design of an integrated circuit from requirement analysis through to implementation.

Teaching periods
Location
Start and end dates
Last self-enrolment date
Census date
Last withdraw without fail date
Results released date

Learning outcomes

On successful completion of this unit students will be able to:

  1. Design, troubleshoot, simulate, analyze and synthesize digital integrated circuits using hardware description language such as VHDL, Verilog, etc. (K2, K3, K4, S1, S2, S3)
  2. Implement and test designed logical functions on a configurable integrated circuit. (K2, K3, K4, S1, S2, S3)
  3. Apply the working principles of digital integrated circuits to interpret, analyze and address design-related problems. (K2, K3, K4, S1, S2, S3)

Teaching methods

Sarawak

Type Hours per week Number of weeks Total (number of hours)
On-campus
Lecture		 2.00  12 weeks  24
On-campus
Practical		 2.00  12 weeks  24
Online
Directed Online Learning and Independent Learning		 1.00 12 weeks  12
Unspecified Activities
Independent Learning		 7.50  12 weeks  90
TOTAL     150

Assessment

Type Task Weighting ULOs
Practical Assignment Individual  60 - 80% 1,2
Test Individual  20 - 40%  3

Content

  • Microelectronics design methodologies (ASIC and FPGA)
  • Issues involved in high level synthesis
  • Hardware description language: VHDL, Verilog, etc.
  • VHDL modeling techniques: structural and behavioral models
  • System implementation strategies
  • State machine design, description, and synthesis using VHDL and Verilog
  • Hardware testing, fault modeling, fault test generation, D algorithm, BIST, JTAG and design for testability
  • Design methodology for high level synthesis
  • Partitioning in high-level synthesis
  • Algorithmic synthesis
  • Scheduling formulation and allocation

Study resources

Reading materials

A list of reading materials and/or required textbooks will be available in the Unit Outline on Canvas.