VLSI Digital Signal Processing Systems

EEE80003 12.5 Credit Points Hawthorn


  • One Semester or equivalent

Contact hours

  • 60 hours

On-campus unit delivery combines face-to-face and digital learning.


Assumed Knowledge
VHDL coding

Aims and objectives

This unit of study aims to introduce you to DSP-related algorithms, hardware transformations and architecture designs for ASIC/SoC real time implementations. Design transformation techniques covering pipelining, parallelisation, retiming, unfolding and folding , bit and digit-level processing implementations will be covered in detail with strong emphasis on low-power design and high speed implementation.

Unit Learning Outcomes (ULO)

Students who successfully complete this unit will be able to:

1. Design and implement digital filters in Direct Form I & II as well as traversal implementation. (K2, K3, S1, S2, S3)
2. Apply pipelining and retiming to DSP circuits to improve performance. (K2, K3, K4, K6, S1, S2, S3)
3. Apply and construct unfolded and folded DSP circuits to meet performance requirements. (K2, K3, K4, K6, S1, S2, S3)
4. Apply folding transformation on a given DSP circuit to share (reduce) the number of arithmetic elements. (K2, K3, K4, K6, S1, S2, S3)
5. Design DSP circuits with algorithmic strength reduction. (K2, K3, K4, K6, S1, S2, S3)
6. Design and implement bit/digit-level architectures. (K2, K3, K4, K6, S1, S2, S3)
7. Design low power DSP circuits (K3, K4, K6, S1, S2, S3)