Overview

This unit aims to develop the required engineering skills to design and implement an integrated circuit design with emphasis on the front-end design skills. The objectives of this unit are to expose students to techniques and design methodology in Integrated Circuit. Students will develop skills in Modelling, simulation, verification, testing and implementation using industry standard EDA tools. Upon satisfactory completion of this subject, students should be able to carry out the design of an integrated circuit from requirement analysis through to implementation.

Requisites

Teaching Periods
Location
Start and end dates
Last self-enrolment date
Census date
Last withdraw without fail date
Results released date
Semester 1
Location
Hawthorn
Start and end dates
26-February-2024
26-May-2024
Last self-enrolment date
10-March-2024
Census date
31-March-2024
Last withdraw without fail date
12-April-2024
Results released date
02-July-2024

Learning outcomes

Students who successfully complete this unit will be able to:

  • Explain and appreciate the design flow of an integrated circuit and its constraints and implications (K2, K3, K4)
  • Construct, analyse, simulate and synthesise VHDL codes for complex digital systems and appreciate the impact of coding style on simulation and synthesis (K2, K3, K4, S1, S2, S3)
  • Apply different design implementations incorporating faults simulation, and testing strategies of IC circuits (K2, K3, K4, S1, S2, S3)
  • Analyse the designed circuits both independently and collaboratively with other teams in terms of circuit optimisation (K2, K3, S1, S2, S3)
  • Explore, and apply effective ways to design a testable integrated circuit (K2, K3, K4, S1, S2, S3)
  • Apply behavioural algorithms to optimise top level design (K2, K3, K4, S1, S2, S3)

Teaching methods

Hawthorn

Type Hours per week Number of weeks Total (number of hours)
On-campus
Lecture
4.00 12 weeks 48
On-campus
Lab
1.00 12 weeks 12
Unspecified Activities
Independent Learning
7.50 12 weeks 90
TOTAL150

Assessment

Type Task Weighting ULO's
ExaminationIndividual 60% 1,3,4,5,6 
Practical AssignmentIndividual 40% 2,4,5,6 

Hurdle

As the minimum requirements of assessment to pass a unit and meet all ULOs to a minimum standard, an undergraduate student must have achieved:

(i) An aggregate mark of 50% or more, and(ii) Obtain at least 40% in the final exam, and(iii) Obtain at least 40% of the possible marks for the laboratory hurdle.Students who do not successfully achieve hurdle requirements (ii) and (iii) will receive a maximum of 45% as the total mark for the unit.

Content

  • Microelectronics design methodologies (ASIC and FPGA)
  • Issues involved in high level synthesis
  • Hardware description language VHDL
  • VHDL modeling techniques: structural and behavioral models
  • System implementation strategies
  • State machine VHDL description and synthesis
  • Hardware testing, fault modeling, fault test generation, D algorithm, BIST, JTAG and design for testability
  • Design methodology for high level synthesis
  • Partitioning in high-level synthesis
  • Algorithmic synthesis
  • Scheduling formulation and allocation

Study resources

Reading materials

A list of reading materials and/or required textbooks will be available in the Unit Outline on Canvas.