HDL and High Level Synthesis

• Graduates are capable in their chosen professional areas.
• Graduates operate effectively in work and community situations.
• Graduates are adaptable and manage change.

The unit will focus on design methodology, hardware modelling and high level synthesis. Students will develop hands-on experience in design using FPGAs. The subject will be supported by industry standard EDA tools for design, synthesis, simulation, verification and implementation. The unit contents are as follows:

• Hardware Modelling and design flow, Features requirements of Hardware Languages (structural and behavioural), Abstract Models, Compilation and Optimisation Techniques. Hardware Description Language VHDL and/or Verilog.
• Architectural – Level Synthesis and Optimisation Modelling, the Fundamental architectural synthesis problems, Area and performance estimation, Data path and Control Unit Synthesis, Synthesis of Pipelined Circuits.
• Synthesis Techniques: Logic synthesis and optimisation. FPGAs synthesis, folding and partitioning. Multi-level logic synthesis techniques: Structured layout styles, Local and Global transformations. State machine synthesis techniques. High level synthesis techniques: Strategies for high level synthesis, Scheduling and allocation operations. High-level optimisations. Realisation using FPGAs and CPLDs. Coding standards.
• Industry Standard EDA Tools.