HDL and High Level Synthesis
Duration
- 1 Semester
Contact hours
- 48 hours
On-campus unit delivery combines face-to-face and digital learning.
2021 teaching periods
Hawthorn
| Higher Ed. Semester 1 | ||
|---|---|---|
Dates: Results: Last self enrolment: Census: Last withdraw without fail: |
Prerequisites
NilCorequisites
NilAims and objectives
To expose students to the advanced HDL design techniques and methodology and industrial standard EDA tools in electronic design. The unit will also allow students to gain hands-on experience with the most recent digital design techniques.
Courses with unit
A unit of study in the
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Unit information in detail
- Teaching methods, assessment, general skills outcomes and content.
Teaching methods
Lectures, Labs, Tutorials
Assessment
Assignment 10%, Experiments 30%, Examination 60%
General skills outcomes
- Graduates are capable in their chosen professional areas.
- Graduates operate effectively in work and community situations.
- Graduates are adaptable and manage change.
Content
The unit will focus on design methodology, hardware modelling and high level synthesis. Students will develop hands-on experience in design using FPGAs. The subject will be supported by industry standard EDA tools for design, synthesis, simulation, verification and implementation. The unit contents are as follows:
- Hardware Modelling and design flow, Features requirements of Hardware Languages (structural and behavioural), Abstract Models, Compilation and Optimisation Techniques. Hardware Description Language VHDL and/or Verilog.
- Architectural – Level Synthesis and Optimisation Modelling, the Fundamental architectural synthesis problems, Area and performance estimation, Data path and Control Unit Synthesis, Synthesis of Pipelined Circuits.
- Synthesis Techniques: Logic synthesis and optimisation. FPGAs synthesis, folding and partitioning. Multi-level logic synthesis techniques: Structured layout styles, Local and Global transformations. State machine synthesis techniques. High level synthesis techniques: Strategies for high level synthesis, Scheduling and allocation operations. High-level optimisations. Realisation using FPGAs and CPLDs. Coding standards.
- Industry Standard EDA Tools.
Study resources
- Text books and recommended reading.
Text books
The lecturer will provide appropriate reading material.
Appropriate IEEE/IEE Journal Papers
Chang, KC, Digital Systems Design with VHDL and Synthesis, IEEE, 1999
Appropriate IEEE/IEE Journal Papers
Chang, KC, Digital Systems Design with VHDL and Synthesis, IEEE, 1999
Recommended reading
Dewey, AM, Analysis and Design of Digital Systems with VHDL, PWS Kent, 1996.
Jerraya, AA, Ding, H & Kission, P, Behavioral Synthesis and Component Reuse with VHDL, Kluwer, 1996.
Jerraya, AA, Ding, H & Kission, P, Behavioral Synthesis and Component Reuse with VHDL, Kluwer, 1996.